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Design-Reuse3h
NVM EEPROM NeoEE in TSMC (180nm, 160nm, 130nm)
eMemory's NeoEE IP is a cost-effective embedded EEPROM solution for both foundries & customers. No additional masks are required, and NeoEE gives foundry and customer many advantages such as fast time ...
Design-Reuse3h
65nm FTP Non Volatile Memory for Standard CMOS Logic Process
NSCore's PermSRAM(R) is the only embedded CMOS, one time programmable (OTP), non-volatile RAM IP of its kind, utilizing the 'hot carrier effect' to trap charge in the sidewall spacer of the gate.
Design-Reuse12h
5G Ultra low power Sub-6 GHz RF Transceiver IP
This is a 3GPP compliant 5G Sub-6GHz RF Transceiver IP optimized for cellular application. It integrates all the necessary RF/analog/mixed signal functions for a 3GPP Universal/5G/4G/3G 2x2 ...
Design-Reuse12h
E-Band Front-End Module 71 GHz to 86 GHz
The WEA7186F55 is a front end for wireless microwave transceivers operating in the E-Band. Implemented in a ST Micro Silicon Germanium B55 process. The WEA7186F55 integrates a LNA path, a Power ...
Design-Reuse12h
TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and ...
Design-Reuse12h
Low frequency 32-kHz RC oscillator optimized for low power
The Always-On domain, over which the power islets emerge, requires a specific panoply of voltage regulators and clocks. The availability of extremely low power oscillators is therefore a must. In low ...
Design-Reuse12h
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits View Single Port Register File compiler - Memory ...
Design-Reuse12h
USB 2.0 Digital Controller IP
The Synopsys USB 2.0 Controllers support Hi-Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation based on USB specification from the USB Implementer Forum. The Synopsys USB 2.0 ...
Design-Reuse15h
14-bit, 300 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ADC ...
Design-Reuse15h
800MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
The SM-CTDSM-800M is a 12-bit continuous-time delta-sigma (CTΔΣ) analog-to-digital converter IP. By leveraging Seamless’ patented Switched-Mode Signal Processing (SMSP) technology, our ADC seamlessly ...
Design-Reuse15h
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems.