This is a 3GPP compliant 5G Sub-6GHz RF Transceiver IP optimized for cellular application. It integrates all the necessary RF/analog/mixed signal functions for a 3GPP Universal/5G/4G/3G 2x2 ...

The WEA7186F55 is a front end for wireless microwave transceivers operating in the E-Band. Implemented in a ST Micro Silicon Germanium B55 process. The WEA7186F55 integrates a LNA path, a Power ...

Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits View Single Port Register File compiler - Memory ...

The ODT-ADP-14B1P2G-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ADC ...

The SM-CTDSM-800M is a 12-bit continuous-time delta-sigma (CTΔΣ) analog-to-digital converter IP. By leveraging Seamless’ patented Switched-Mode Signal Processing (SMSP) technology, our ADC seamlessly ...

The IP is a 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC). It comprises of a second-order discrete-time modulator followed by a third-order CIC decimation filter with programmable output ...

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems.

AFE24B19KS180NM is low-power, low noise 8-channel fully differential or 16 pseudo differential inputs, 24-bit, (ΔΣ) analog-to-digital converters (ADCs) with an integrated low-drift internal reference ...

The A12B50M is an ultra low-power, pipeline analog to digital converter (ADC) intellectual property (IP) design block. It has 12-bit resolution and a sampling rate of up to 50 megasamples per second ...

The A12B5G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a hybrid successive approximation register (SAR) ADC, with a 12-bit resolution, ...

The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications.

Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC ...